AD5530 datasheet(4/16 Pages) AD

4 / 16 page

REV. 0

–4–

AD5530/AD5531

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;

RL = 5 k

Ω and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)

SCLK

SYNC

SDIN

LDAC*

CLR

LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED

DB15

DB14

DB11

DB0

MSB

LSB

t12

t10

t11

Figure 1. Timing Diagram for Standalone Mode

STANDALONE TIMING CHARACTERISTICS1, 2

Parameter

Limit at TMIN, TMAX

Unit

Description

fMAX

MHz max

SCLK Frequency

140

ns min

SCLK Cycle Time

ns min

SCLK Low Time

ns min

SCLK High Time

ns min

SYNC to SCLK Falling Edge Setup Time

ns min

SCLK Falling Edge to

SYNC Rising Edge

ns min

Min

SYNC High Time

ns min

Data Setup Time

ns min

Data Hold Time

ns min

SYNC High to LDAC Low

t10

ns min

LDAC Pulsewidth

t11

ns min

LDAC High to SYNC Low

t12

ns min

CLR Pulsewidth

1Guaranteed by design. Not production tested.

2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns

(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.

Specifications subject to change without notice.

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