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A3980KLP bảng dữ liệu(PDF) 6 Page - Allegro MicroSystems |
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A3980KLP bảng dữ liệu(HTML) 6 Page - Allegro MicroSystems |
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6 / 18 page ![]() Automotive DMOS Microstepping Driver with Translator A3980 5 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ.1 Max. Units Current Control Blank Time tBLANK RT = 56 K , CT = 680 pF 700 950 1200 ns Fixed Off Time tOFF RT = 56 K , CT = 680 pF 30 38 46 μs Mixed Decay Trip Points PFDH PFDL –– 0.60 VDD 0.21 VDD – V Crossover Dead Time tDT – 100 475 800 ns Recommended Reference Input Voltage VREF – 0.8 – 4V Reference Input Current2 IREF – –3 0 3 μA Current Trip-Level Error3 errI 2 V < VREF < 4 V, %ITripMAX = 38% 2 V < VREF < 4 V, %ITripMAX = 70% 2 V < VREF < 4 V, %ITripMAX = 100% –– ±15 ±10 ±5 % Thermal Protection Thermal Shutdown TSD – 160 170 180 ºC Thermal Shutdown Hysteresis TSDH –– 15 – ºC Diagnostics Max VDS on High-Side Bridge FETs VDSHT Sampled after tBLANK + tSCT – 1.5 – V Max VDS on Low-Side Bridge FETs VDSLT Sampled after tBLANK + tSCT – 1.5 – V VDS Fault Measurement Delay tSCT –– 700 – ns Minimum Load Current IOC w.r.t. ITRIPMAX at Home position – 35 – % VBB Overvoltage Lockout VOVB VBB rising 32 34 36 V VBB Overvoltage Lockout Hysteresis VOVBH – 2 – 4V VREG Undervoltage Lockout VUVR VREG falling 5.3 5.7 6.0 V VDD Enable Threshold VUVD VDD rising 2.45 2.7 2.95 V VDD Enable Threshold Hysteresis VUVDH – 50 100 – mV ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to +150ºC, VBB = 14 V, VDD = 3.0 to 5.5 V (unless otherwise noted) 1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2Negative current is defined as coming out of (sourcing from) the specified device pin. 3errI = (ITrip – IProg) ⁄ IProg, where IProg = %ITripMAX ×ITripMAX. |
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