TABLE 6. FastLock Timeout Counter Value Programming

Timeout

3

7

11

15

19

23

27

31

35

•

59

63

(# PD Cycles)

(Note 8)

F11

0

1

0101010

•

01

(4)

F12

0

0

1100110

•

11

(8)

F13

0

0

0011110

•

11

(16)

F14

0

0

0000001

•

11

(32)

Note 8: The timeout counter decrements after each phase detector comparison cycle.

1.4 SERIAL DATA INPUT TIMING

1.5 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

DS100127-9

Notes: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

DS100127-10

Notes: Phase difference detection range: −2

π to +2π

The Phase Detector Polarity F[6] = HIGH

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