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IR2010S bảng dữ liệu(PDF) 2 Page - International Rectifier |
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IR2010S bảng dữ liệu(HTML) 2 Page - International Rectifier |
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2 / 16 page ![]() 2 www.irf.com IR2010(S) & (PbF) (Please refer to the Design Tip DT97-3 for more details). Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS. Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD. Symbol Definition Min. Max. Units VB High side floating supply absolute voltage VS + 10 VS + 20 VS High side floating supply offset voltage Note 1 200 VHO High side floating output voltage VS VB VCC Low side fixed supply voltage 10 20 VLO Low side output voltage 0 VCC VDD Logic supply voltage VSS + 3 VSS + 20 VSS Logic supply offset voltage -5 (Note 2) 5 VIN Logic input voltage (HIN, LIN & SD) VSS VDD TA Ambient temperature -40 125 °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 24 and 25. V Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units VB High side floating supply voltage -0.3 225 VS High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side fixed supply voltage -0.3 25 VLO Low side output voltage -0.3 VCC + 0.3 VDD Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 VIN Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns PD Package power dissipation @ TA ≤ +25°C (14 lead DIP) — 1.6 (16 lead SOIC) — 1.25 RTHJA Thermal resistance, junction to ambient (14 lead DIP) — 75 (16 lead SOIC) — 100 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 °C/W W V °C |
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