ADV7312 datasheet(51/84 Pages) AD

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ADV7312

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Adaptive Filter Control Application

Figures 44 and 45 show typical signals to be processed by the

adaptive filter control block.

: 692mV

@: 446mV

: 332ns

@: 12.8ms

Figure 44. Input Signal to Adaptive Filter Control

: 692mV

@: 446mV

: 332ns

@: 12.8ms

Figure 45. Output Signal after Adaptive Filter Control

The following register settings were used to obtain the results

shown in Figure 45, i.e., to remove the ringing on the Y signal.

Input data was generated by an external signal source.

When changing the adaptive filter mode to Mode B [Address 15h,

Bit 6], the following output can be obtained:

: 674mV

@: 446mV

: 332ns

@: 12.8ms

Figure 46. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the

internally generated cross hatch test pattern and toggling the

adaptive filter control bit [Address 15h, Bit 7].

Table XV.

Address

00h

FCh

01h

38h

02h

20h

10h

00h

11h

85h

15h

80h

20h

00h

38h

ACh

39h

9Ah

3Ah

88h

3Bh

28h

3Ch

3Fh

3Dh

64h

Table XIV.

Address

00h

FCh

01h

38h

02h

20h

10h

00h

11h

81h

15h

80h

20h

00h

38h

ACh

39h

9Ah

3Ah

88h

3Bh

28h

3Ch

3Fh

3Dh

64h

All other registers are set as normal/default.

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