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AD9821

Complete 12-Bit 40 MSPS

Imaging Signal Processor

FEATURES

Differential Sensor Input with 1 V p-p Input Range

0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)

Low Noise Optical Black Clamp Circuit

Analog Preblanking Function

12-Bit 40 MSPS A/D Converter (ADC)

3-Wire Serial Digital Interface

3 V Single-Supply Operation

Low Power: 150 mW @ 3 V Supply

48-Lead LQFP Package

APPLICATIONS

Digital Still Cameras Using CMOS Imagers

Industrial/Scientific Imaging

FUNCTIONAL BLOCK DIAGRAM

DATACLK

BAND GAP

REFERENCE

DOUT

VIN+

PBLK

VRT

VRB

0dB ~ 36dB

AVDD

DVDD

DVSS

AVSS

DRVDD

DRVSS

10

8

DIGITAL

INTERFACE

SDATA

SCK

SL

CLPOB

12

VGA

CLP

AD9821

INTERNAL

REGISTERS

12-BIT

ADC

BLK CLAMP

LEVEL

VIN–

BYP1

SHA

+

–

GENERAL DESCRIPTION

The AD9821 is a complete analog signal processor for imaging

applications that do not require Correlated Double Sampling

(CDS). It features a 40 MHz single-channel architecture designed

to sample and condition the outputs of CMOS imagers and CCD

arrays already containing on-chip CDS. The AD9821’s signal

chain consists of a differential input sample-and-hold amplifier

(SHA), digitally controlled variable gain amplifier (VGA), black

level clamp, and a 12-bit ADC.

The internal registers are programmed through a 3-wire serial

digital interface. Programmable features include gain adjust-

ment, black level adjustment, and power-down modes.

The AD9821 operates from a single 3 V power supply, typically

dissipates 150 mW, and is packaged in a 48-lead LQFP.