VREF datasheet(14/19 Pages) AKM

14 / 19 page

ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 14 -

Power-down mode

The AK5352 has to be reset once by bringing

PD "L" upon power-up. All internal registers of the digital filter

and so on in the AK5352 are reset by this operation. When exiting the power-down mode(

PD="H"), the

internal timing starts clocking by first MCLK "

↑"(rising edge). In master mode internal counter starts at once, in

slave mode internal counter starts after synchronizing with the first rising edge of LRCK. The serial output data

is available after 516 counting clock of LRCK cycle.

Asynchronization-reset

In slave mode, if the phase difference between LRCK and internal control signals is larger than +1/16

∼ -1/16

of word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first

rising edge of LRCK.

High Pass Filter(HPFE pin)

The AK5352 has a Digital High Pass Filter(HPF) for DC-offset cancel. When HPFE pin goes "H", HPF is

enabled. The cut-off frequency of the HPF is 1Hz(@fs=48kHz). It also scales with the sampling frequency(fs).

The HPF can be disabled by bringing HPFE pin "L". In this case, the AK5352 has the DC-offset of a few mV.

VREF bảng dữ liệu(PDF) 14 Page - Asahi Kasei Microsystems