ADUC831BCP datasheet(21/76 Pages) AD

21 / 76 page

REV. 0

ADuC831

–21–

Table V. ADCCON3 SFR Bit Designations

Bit

Name

Description

ADCCON3.7 BUSY

The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or

calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.

ADCCON3.6 GNCLD

Gain Calibration Disable Bit

Set to “0” to Enable Gain Calibration.

Set to “1” to Disable Gain Calibration.

ADCCON3.5 AVGS1

Number of Averages Selection Bits

ADCCON3.4 AVGS0

This bit selects the number of ADC readings averaged during a calibration cycle.

AVGS1

AVGS0

Number of Averages

ADCCON3.3 RSVD

Reserved. This bit should always be written as “0.”

ADCCON3.2 RSVD

This bit should always be written as “1” by the user when performing calibration.

ADCCON3.1 TYPICAL

Calibration Type Select Bit.

This bit selects between Offset (zero-scale) and gain (full-scale) calibration.

Set to 0 for Offset Calibration.

Set to 1 for Gain Calibration.

ADCCON3.0 SCAL

Start Calibration Cycle Bit.

When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration

cycle is completed.

ADCCON3 – (ADC Control SFR #3)

The ADCCON3 register controls the operation of various calibra-

tion modes as well as giving an indication of ADC busy status.

SFR Address:

F5H

SFR Power-On Default Value:

00H

Bit Addressable:

ADUC831BCP bảng dữ liệu(PDF) 21 Page - Analog Devices

ADUC831BCP bảng dữ liệu(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

bảng dữ liệu tải về

Link URL