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WM8510GEDS/RV bảng dữ liệu(PDF) 9 Page - Wolfson Microelectronics plc

tên linh kiện WM8510GEDS/RV
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WM8510GEDS/RV bảng dữ liệu(HTML) 9 Page - Wolfson Microelectronics plc

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WM8510
w
PP Rev 1.2 December 2004
9
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DCVDD=1.62V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25
oC, Slave Mode fs = 48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
TMCLKY
Tbd
ns
MCLK duty cycle
TMCLKDS
60:40
40:60
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)



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