WM8772 datasheet(52/70 Pages) WOLFSON

52 / 70 page

WM8772EFT – 32 PIN TQFP

Production Data

PD Rev 4.1 October 2004

2S MODE

In I

2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of

BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on

the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge

of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 45 I

2S Mode Timing Diagram

DSP EARLY MODE

In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the

second rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC

channels 2 and 3 data follow DAC channel 1 left data (Figure 46).

DACLRC

DACBCLK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 3

RIGHT

NO VALID DATA

1 BCLK

Figure 46 DSP Early Mode Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of

ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 47)

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