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VBUS54FD-SD1 bảng dữ liệu(PDF) 2 Page - Vishay Siliconix |
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VBUS54FD-SD1 bảng dữ liệu(HTML) 2 Page - Vishay Siliconix |
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2 / 6 page ![]() VBUS54FD-SD1 www.vishay.com Vishay Semiconductors Rev. 1.1, 20-Sep-16 2 Document Number: 82665 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE The VBUS54FD-SD1 is a four-line ESD-protection device with the characteristic of a Z-diode with a high ESD-immunity and a very low capacitance which makes it usable for high frequency applications like USB 2.0, USB 3.0 or HDMI. With the VBUS54FD-SD1 four high speed data lines can be protected against transient voltage signals like ESD (Electro Static Discharge). Connected to the data line (pin 1, 3 and pin 4, 5) and to ground (pin 2) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping behavior of the VBUS54FD-SD1 is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5.5 V. Pin configuration: • Pin 2 is the central ground pin and has to be connected to ground • Pin 1, 3 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2- FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB 2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD-protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the VBUS54FD-SD1 is placed on top without any vias or loops. ELECTRICAL CHARACTERISTICS (pin 1, 3, 4 or 5 to pin 2) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Protection paths Number of lines which can be protected Nchannel -- 4 lines Reverse stand-off voltage Max. reverse working voltage VRWM -- 5.5 V Reverse voltage at IR = 0.1 μA VR 5.5 - - V Reverse current at VRWM = 5.5 V IR - < 1 nA 0.1 μA Reverse breakdown voltage at IR = 1 mA VBR 6.9 7.5 8.7 V Reverse clamping voltage at IPP = 1 A VC -9.5 11 V at IPP = IPPM = 3 A VC - 12.9 15 V Forward clamping voltage at IPP = 1 A VF -1.8 2.2 V at IPP = 3 A VF -3 4 V Capacitance at VR = 0 V; f = 1 MHz CD -0.9 1 pF at VR = 3.3 V; f = 1 MHz - 0.9 1 pF Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 8 A VC-TLP -18- V Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 16 A VC-TLP -24- V Dynamic resistance Transmission Line Pulse (TLP); tp = 100 ns VC-TLP -0.93- 22736 13 2 5 4 Receiver Transmitter 1 2 3 5 4 22737 |
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