STK17TA8

February 2004

6

Document Control # ML0023 rev 0.3

MODE SELECTION

Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

Note n: While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes.

Note o: I/O state depends on the state of G. The I/O table shown assumes G low.

E

W

G

MODE

I/O

POWER

NOTES

H

X

X

X

Not Selected

Output High Z

Standby

L

H

L

X

Read SRAM

Output Data

Active

L

L

X

X

Write SRAM

Input Data

Active

LHL

4E38

B1C7

83E0

7C1F

703F

8B45

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore Inhibit

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

m, n, o

LHL

4E38

B1C7

83E0

7C1F

703F

4B46

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore inhibit off

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

m, n, o

LHL

4E38

B1C7

83E0

7C1F

703F

8FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Store

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

2

m, n, o

LHL

4E38

B1C7

83E0

7C1F

703F

4C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Recall

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

m, n, o