CAT64LC40 datasheet(7/12 Pages) CATALYST

tên linh kiện	CAT64LC40

Giải thích chi tiết về linh kiện	1K/2K/4K-Bit SPI Serial EEPROM

PDF	12 Pages

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nhà sản xuất	CATALYST [Catalyst Semiconductor]

Trang chủ	http://www.catalyst-semiconductor.com

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7 / 12 page

Discontinued

Parts

CAT64LC10/20/40

Doc. No. 1021, Rev. C

a 16-bit data field is also required following the 8-bit

address field.

The CAT64LC10/20/40 requires an active LOW

CS in

order to be selected. Each instruction must be preceded

by a HIGH-to-LOW transition of

CS before the input of

the 4-bit start sequence. Prior to the 4-bit start sequence

(1010), the device will ignore inputs of all other logical

sequence.

Figure 4. Write Instruction Timing

Figure 5. Ready/

BUSY

BUSY Status Instruction Timing

Read

Upon receiving a READ command and address (clocked

into the DI pin), the DO pin will output data one tPD after

the falling edge of the 16th clock (the last bit of the

address field). The READ operation is not affected by

the RESET input.

Write

After receiving a WRITE op code, address and data, the

device goes into the AUTO-Clear cycle and then the

* Please check instruction set table for address

RESET

10100100

ADDRESS*

D15

RDY/

BUSY

RESET

WRITE INSTRUCTION

NEXT INSTRUCTION

HIGH

LOW

RDY/

BUSY

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