AS1124 datasheet(15/21 Pages) ETC2

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AS1124

Akros Silicon, inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



www.AkrosSilicon.com

DC-DC CONTROLLER

Overview

The DC-DC architecture is a current-mode controller

which can be configured with external component changes

to flyback, forward, or non-synchronous low-side switch

buck topologies. Both non-isolated and isolated topologies

are supported.

As part of full system level solution for EMI, Akros has

focused significant effort in reducing switching noise in the

integrated power converters through unique techniques of

balancing the signaling of the FET drivers and reducing

ground bounce by minimizing the dV/dt switching noise.

The integrated DC-DC controller operates from a switched

input voltage (VDD48O) and includes soft-start and

current limiting. Once input power is applied and enable

signals are asserted, the DC-DC controller starts up. The

controller provides gate control signals to external

switching MOSFETs, and uses an external resistor to

sense the transformer primary current.

The DC-DC controller includes programmable soft start,

80% maximum duty cycle, fixed switching frequency and a

voltage output error amplifier.

Current-Limit/Current Sense

The DC/DC controller provides cycle-by-cycle current

limiting to ensure that transformer primary current limits

are not exceeded. In addition, the maximum average

current in the transformer primary is set by internal duty

cycle limits.

Low Load Current Operation

The internal circuitry detects a low output power condition

and puts the DC-DC Controller into a discontinuous

current operation (DCM) mode.

Compensation and Feedback

For isolated applications, loop compensation and output

voltage feedback is generally provided by an opto-isolator

circuit, and the FB pin is shorted to ground. In these

applications, the COMP pin is pulled up to 4.8V

(nominally) by an internal current source.

This pull-up can be the termination for an opto-isolator, or

an additional resistor can be used in parallel.

For non-isolated applications, a resistive divider network

senses the output voltage and is applied directly to the FB

pin. The internal error amplifier is connected to a 1.5V

reference voltage and the control loop will servo the FB

pin to this voltage.

A capacitive/resistive network

connected to the COMP pin provides loop compensation.

Soft-Start inrush current limit

The internal circuitry automatically ramps up the inrush

current by limiting the maximum current allowed in the

transformer primary magnetizing inductance per clock

cycle. The amount of time required to perform a soft start

cycle is determined by the CSS capacitor. A CSS

capacitor of 330nF provides approximately 7ms of soft

startup ramp time.

AUXILIARY POWER OPTION

The Auxiliary Power Option allows the AS1124 to be

powered from a DC power source, other than the Ethernet

line. Examples of DC sources are AC/DC wall adapters,

batteries, or solar cells. This feature may also be used, to

supply power that exceeds the load capacity of the PSE,

or in non-PoE systems.

DC-DC CONVERTER TOPOLOGIES

Flyback vs. Forward Operation

The DC-DC controller can be configured in several

different operational topologies and in either isolated or

non-isolated configurations.

The FLYBACK mode is

chosen when a minimum number of external components

is desired or there is a large step-down and the output

voltage is < 7V. The FORWARD mode is chosen with

lower output noise and higher efficiency is desired. The

FLYBACK mode is shown in figure 8 and the FORWARD

mode in shown in figure 9, both in isolated configurations.

Buck Operation

The BUCK mode is shown in figure 10. The buck mode is

used only in non-isolated applications. The BUCK mode

uses an inductor instead of a transformer and therefore

has the smallest overall footprint. Figure 10 shows the

BUCK converter in a non synchronous operation where

the output voltage is referenced to VDD48O. Since the FB

voltage is ground referenced, the feedback signal must be

level shifted back down to ground. This is accomplished

by the two PNP transistors and the associated resistors.

Primary Switching Topology

The DC-DC controller uses a two-switch topology to

minimize noise, maximize efficiency and reduce the

breakdown requirements for the switching transistors.

During OFF time and when the core is being reset, a

snubbing circuit, consisting of parallel Schottky diodes,

directs the transformer magnetizing current into the bulk

storage capacitors connected to VDD48O. This additional

snubbing circuitry minimizes the ringing that can occur on

the primary winding of the power transformer. In single

switch topologies, the maximum VDS are approximately

2.5X VDD48O and there can be significant ringing during

OFF time, when the transformer core is being reset.

Again, snubbing circuitry is used to dissipate the ringing

noise that occurs during the switching transitions.

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