CS7410 datasheet(31/39 Pages) CIRRUS

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CS7410

DS553PP1

4.4

SDRAM / DRAM Interface

These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths of 4

to 16 bits are supported. The CS7410 supports word or block transfers (partial word transfers are not re-

quired). Table 10 gives instructions on how to interface to any particular configuration of SDRAM. Table 11

gives pin definitions for interfacing to EDO DRAM.

SER2_CS

Chip select for 4-wire serial port (output if master, input if

slave mode). Can also be used as bidirectional ready line.

SER3_CLK

Clock output

SER3_DO

Data output – up to 32 bits per transfer.

SER3_DI

Data input – up to 96 bits per transfer.

SER3_SS0

Slave select for first peripheral (programmable polarity)

SER3_SS1

Slave select for second peripheral (programmable polar-

ity)

Table 9. Serial Interface Pins (Continued)

Signal Name

Type

Description

3, 4, 5, 6, 7, 8, 9,

10, 11, 13, 15, 20,

21, 22, 23, 24

DRAM

Data[15..0]

Memory Data Bus.

25, 26, 27, 28,

29, 30, 31, 32,

33, 34, 35, 36

DRAM

Address[11..0]

Memory Address Bus. Connect in order starting with

DR_Addr[0] to all RAM address pins not already connected

to DR_BS_L or DR_AP.

DR_RAS_L

Memory Row Address Strobe

DR_CAS_L

Memory Column Address Strobe

M_WE_L

Memory Write Enable

DR_CKO

SDRAM Clock

DR_CKE

SDRAM Clock Enable

DR_BS_L

Bank Selection. Always connect to RAM BS or BS0 pin.

M_AP_OE

Memory Auto Pre-charge. Always connect to RAM AP pin.

Table 10. SDRAM Interface

Signal Name

Type

Description

3, 4, 5, 6,

7, 8,

9, 10,

11, 13,

15, 20, 21, 22,

23, 24

DRAM

Data[15..0]

Memory Data Bus.

Table 11. EDO DRAM Interface

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