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LM98501 bảng dữ liệu(PDF) 18 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện LM98501
Giải thích chi tiết về linh kiện  10-Bit, 27 MSPS Camera Signal Processor
PDF  24 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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LM98501 bảng dữ liệu(HTML) 18 Page - National Semiconductor (TI)

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Register Data (Continued)
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
Register Name Analog Offset 3
Address
7 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:0]
Signed Analog
Offset
Digital representation of the
analog offset to be applied to
the input of the PGA. See
“Analog Offset” on page 15.
COLOR FILTER ARRAY REGISTERS
Register Name Color Filter Array Configuration 0
Address
8 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:6]
Line0:Pixel3
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 3 of the
CFA pattern are stored.
[5:4]
Line0:Pixel2
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 2 of the
CFA pattern are stored.
[3:2]
Line0:Pixel1
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 1 of the
CFA pattern are stored.
[1:0]
Line0:Pixel0
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 0 of the
CFA pattern are stored.
Register Name Color Filter Array Configuration 1
Address
9 Hex
Type
Read/Write
Reset Value
0000 0000 Binary
Bit
Bit Symbol
Description
[7:6]
Line1:Pixel3
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 3 of the
CFA pattern are stored.
[5:4]
Line1:Pixel2
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 2 of the
CFA pattern are stored.
Bit
Bit Symbol
Description
[3:2]
Line1:Pixel1
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 1 of the
CFA pattern are stored.
[1:0]
Line1:Pixel0
Gain/Offset
2 LSB’s of register
addresses where the gain
and offset for pixel 0 of the
CFA pattern are stored.
Register Name Color Filter Array Definition
Address
A Hex
Type
Read/Write
Reset Value
XXXX 0000 Binary
Bit
Bit Symbol
Description
[3:2]
Line 1 Pixels
Number of pixels in CFA
pattern defined in CFA line
1.
[2:1]
Line 0 Pixels
Number of pixels in CFA
pattern defined in CFA line
0.
OUTPUT BLACK LEVEL REGISTER
Register Name Output Black Level
Address
B Hex
Type
Read/Write
Reset Value
0001 0000 Binary
Bit
Bit Symbol
Description
[7:0]
Black Level
0–256 output black level
digital code value. (see
“Output Black Level” on
page 15)
SOFTWARE CONTROL REGISTERS
Register Name Software Control 0 (Customer)
Address
C Hex
Type
Read/Write
Reset Value
0100 1110 Binary
Bit
Bit Symbol
Description
[7]
Offset Output
Enable
Directs the offset error
calculated by the digital
black level correction loop to
the 10 digital output data
pins.
[6]
Serial Output
Enable
Enables the serial interface
output for reading register
values.
[5:4]
Offset
Integration
Offset integration factor
selection:
00 No Scaling
01 Divide-by-4
10 Divide-by-8
11 Divide-by-16
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