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MPC9772 bảng dữ liệu(PDF) 10 Page - Motorola, Inc

tên linh kiện MPC9772
Giải thích chi tiết về linh kiện  3.3V 1:12 LVCMOS PLL Clock Generator
PDF  16 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC9772 bảng dữ liệu(HTML) 10 Page - Motorola, Inc

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MPC9772
MOTOROLA
10
TIMING SOLUTIONS
SYNC Output Description
The MPC9772 has a system synchronization pulse output
QSYNC. In configurations with the output frequency
relationships are not integer multiples of each other QSYNC
provides a signal for system synchronization purposes. The
MPC9772 monitors the relationship between the A bank and
the B bank of outputs. The QSYNC output is asserted (logic
low) one period in duration and one period prior to the
coincident rising edges of the QA and QC outputs. The duration
and the placement of the pulse is dependent QA and QC output
frequencies: the QSYNC pulse width is equal to the period of
the higher of the QA and QC output frequencies. Figure 6
shows various waveforms for the QSYNC output. The QSYNC
output is defined for all possible combinations of the bank A and
bank C outputs.
fVCO
1:1 Mode
QA
QC
QSYNC
2:1 Mode
QC(
÷2)
QA(
÷6)
QSYNC
3:1 Mode
QA
QC
QSYNC
QA(
÷4)
QC(
÷6)
QSYNC
3:2 Mode
QC(
÷2)
QA(
÷8)
QSYNC
4:1 Mode
QA(
÷6)
QC(
÷8)
QSYNC
4:3 Mode
QA(
÷12)
QC(
÷2)
QSYNC
6:1 Mode
Figure 6. QSYNC Timing Diagram



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