MPC9229

TIMING SOLUTIONS

3

MOTOROLA

Table 1. Pin Configuration

Pin

I/O

Default

Type

Function

XTAL_IN, XTAL_OUT

Analog

Crystal oscillator interface

FOUT, FOUT

Output

LVPECL

Differential clock output

TEST

Output

LVCMOS

Test and device diagnosis output

S_LOAD

Input

0

LVCMOS

Serial configuration control input.

This inputs controls the loading of the configuration latches with the contents of

the shift register. The latches will be transparent when this signal is high, thus the

data must be stable on the high-to-low transition.

P_LOAD

Input

1

LVCMOS

Parallel configuration control input.

This input controls the loading of the configuration latches with the content of the

parallel inputs (M and N). The latches will be transparent when this signal is low,

thus the parallel data must be stable on the low-to-high transition of P_LOAD.

P_LOAD is state sensitive

S_DATA

Input

0

LVCMOS

Serial configuration data input.

S_CLOCK

Input

0

LVCMOS

Serial configuration clock input.

M[0:8]

Input

1

LVCMOS

Parallel configuration for PLL feedback divider (M).

M is sampled on the low-to-high transition of P_LOAD.

N[1:0]

Input

1

LVCMOS

Parallel configuration for Post-PLL divider (N).

N is sampled on the low-to-high transition of P_LOAD

OE

Input

1

LVCMOS

Output enable (active high)

The output enable is synchronous to the output clock to eliminate the possibility of

GND

Supply

Supply

Ground

Negative power supply (GND)

Supply

Supply

positive power supply for correct operation

VCC_PLL

Supply

Supply

PLL positive power supply (analog power supply)

Table 2. Output frequency range and PLL Post-divider N

N

O

di i i

O

f

1

0

Output division

Output frequency range

0

0

1

200 - 400 MHz

0

1

2

100 - 200 MHz

1

0

4

50 - 100 MHz

1

1

8

25 - 50 MHz

Freescale Semiconductor, Inc.

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