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nation of the applied SampCLK and MCLK signals. MCLK is used to

synchronize the applied SampCLK signal. The internal ADC clock

will go low after the falling edge of SampCLK is clocked by a rising

of MCLK. The ADC clock will stay low for two MCLK cycles and

then go high. It will stay high until the next falling edge of SampCLK

is clocked by MCLK. Figure 6 illustrates this SampCLK, MCLK, and

ADC clock timing relationship.

Figure 6: LM9810/20 Relative Event Timing

The LM9810/20 is a densely designed, mixed-signal, monolithic

semiconductor. In creating the timing for the LM9810/20, it must

be considered that internal events, such as ADC sampling, and

output data bus switching can potentially affect coincident events

such as input signal sampling or offset DAC settling. One event

can interfere with another by coupling noise on shared resources

such as the supply lines, internal voltage references, or the silicon

substrate.

To optimize the performance of the LM9810/20, SampCLK should

be timed so that the input signal hold times do not coincide with

output data switching and ADC clock transitions. In other words,

the rising and falling edges of SampCLK should not be placed

close to ADC clock edges or to output data transitions. SampCLK

edges should be at least 20ns away from ADC clock edges to

avoid interference between the ADC and the sampler. SampCLK

edges should also be placed at least 40ns after output data tran-

sition times to avoid transition noise coupling.

Figure 6 is an example of SampCLK timing that will meet these

requirements at the maximum MCLK frequency of 24MHz. In dia-

gram 6, SampCLK transitions occur on MCLK falling edges which

will keep them more than 20ns away from ADC transitions, and

40ns after output data transitions.

MCLK

SampCLK

ADC Clock

(internal)

D5 - D0

b11 - b6

b5 - b0

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