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IP2002 bảng dữ liệu(PDF) 2 Page - International Rectifier

tên linh kiện IP2002
Giải thích chi tiết về linh kiện  Synchronous Buck Synchronous Buck Integrated Power Semiconductors, Drivers & Passives
PDF  12 Pages
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IP2002 bảng dữ liệu(HTML) 2 Page - International Rectifier

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iP2002
All specifications @ 25°C (unless otherwise specified)
Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see
Fig. 8).
Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Supply Voltage
V
DD
4.6
5.0
5.5
V
Input Voltage Range
V
IN
3.0
-
13.2
V
see Figs. 2 & 3
Output Voltage Range
V
OUT
0.9
-
3.3
V
see Figs. 2, 4 & 8
Output Current Range
I
OUT
--
30
A
see Fig. 2
Operating Frequency
fsw
150
-
1000
kHz
see Figs. 2 & 5
Operating Duty Cycle
D
-
-
85
%
Recommended Operating Conditions :
Absolute Maximum Ratings :
Electrical Specifications @ V
DD = 5V (unless otherwise specified) :
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Block Power Loss
P
BLK
-
7.2
8.9
W
V
IN = 12V, VOUT = 1.3V,
Turn On Delay
t
d(on)
-63
-
I
OUT = 30A, fSW = 1MHz
Turn Off Delay
t
d(off)
-26
-
V
IN Quiescent Current
I
Q-VIN
-
-
1.0
mA
Enable = 0V, V
IN = 12V
V
DD Quiescent Current
I
Q-VDD
--
10
µA
Enable = 0V, V
DD = 5V
Under-Voltage Lockout
UVLO
Start Threshold
V
START
4.2
4.4
4.5
V
Hysteresis
V
Hys-UVLO
-
.05
-
Enable
Enable
Input Voltage High
V
IH
2.0
-
-
V
Input Voltage Low
V
IL
-
-
0.8
Power Ready
PRDY
Logic Level High
V
OH
4.5
4.6
-
V
V
DD = 4.6V, ILoad = 10mA
Logic Level Low
V
OL
-
0.1
0.2
V
DD < UVLO Threshold, ILoad = 1mA
PWM Input
PWM
Logic Level High
V
OH
2.0
-
-
V
Logic Level Low
V
OL
-
-
0.8
ns
Parameter
Min
Typ
Max
Units
Conditions
V
IN to PGND
-
-
16
V
V
DD to SGND
-
-
6.0
V
PWM to SGND
-0.3
-
V
DD+0.3
V
not to exceed 6.0V
Enable to SGND
-0.3
-
V
DD+0.3
V
not to exceed 6.0V
Output RMS Current
-
-
30
A
Block Temperature
-40
-
125
°C



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