WM8776 datasheet(19/55 Pages) WOLFSON

19 / 55 page

Product Preview

WM8776

PP Rev 1.91 June 2004

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8776 on the rising edge of

DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and

changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be

sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left

samples and low during the right samples (Figure 13).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 13 Right Justified Mode Timing Diagram

2S MODE

In I

2S mode, the MSB of DIN is sampled by the WM8776 on the second rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on the first falling edge of ADCBCLK following an ADCLRC transition and may be

sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are low during the left

samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 14 I

2S Mode Timing Diagram

DSP EARLY MODE

In DSP early mode, the MSB of DAC left data is sampled by the WM8776 on the second

rising edge on DACBCLK following a DACLRC rising edge. DAC right data follows DAC

channel left data (Figure 15).

WM8776 bảng dữ liệu(PDF) 19 Page - Wolfson Microelectronics plc

WM8776 bảng dữ liệu(HTML) 19 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

bảng dữ liệu tải về

Link URL