ZSC31010 Datasheet

© 2016 Integrated Device Technology, Inc.

4

January 20, 2016

3.3.

Command/Data Bytes Encoding ................................................................................................................24

3.4.

Calibration Sequence .................................................................................................................................25

3.5.

EEPROM Bits .............................................................................................................................................27

3.6.

Calibration Math .........................................................................................................................................29

3.6.1.

Correction Coefficients.........................................................................................................................29

3.6.2.

Interpretation of Binary Numbers for Correction Coefficients ..............................................................30

3.7.

Reading EEPROM Contents ......................................................................................................................34

4

Application Circuit Examples.............................................................................................................................35

4.1.

Three-Wire Rail-to-Rail Ratiometric Output................................................................................................35

4.2.

Absolute Analog Voltage Output ................................................................................................................36

4.3.

Three-Wire Ratiometric Output with Over-Voltage Protection ...................................................................36

4.4.

Digital Output ..............................................................................................................................................37

4.5.

Output Short Protection ..............................................................................................................................37

5

Default EEPROM Settings ................................................................................................................................38

6

Pin Configuration and Package.........................................................................................................................39

7

ESD/Latch-Up-Protection ..................................................................................................................................40

8

Test....................................................................................................................................................................40

9

Quality and Reliability........................................................................................................................................40

10 Customization....................................................................................................................................................40

11 Ordering Codes .................................................................................................................................................41

12 Related Documents...........................................................................................................................................41

13 Definitions of Acronyms.....................................................................................................................................41

14 Document Revision History ...............................................................................................................................42

List of Figures

Figure 2.1

ZSC31010 Block Diagram ...................................................................................................................11

Figure 2.2

DAC Output Timing for Highest Update Rate......................................................................................15

Figure 3.1

General Working Mode ........................................................................................................................18

Figure 3.2

Manchester Duty Cycle........................................................................................................................20

Figure 3.3

19-Bit Write Frame...............................................................................................................................20

Figure 3.4

Read Acknowledge ..............................................................................................................................21

Figure 3.5

Digital Output (NOM) Bridge Readings ...............................................................................................21

Figure 3.6

Digital Output (NOM) Bridge Readings with Temperature ..................................................................22

Figure 3.7

Read EEPROM Contents ....................................................................................................................22

Figure 3.8

Transmission of a Number of Data Packets ........................................................................................22

Figure 3.9

ZACwire™ Output Timing for Lower Update Rates.............................................................................23

Figure 4.1

Rail-to-Rail Ratiometric Voltage Output...............................................................................................35