+5.75 V

25˚C.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 8)

(Note 9)

(Limits)

ISA TIMING CHARACTERISTICS

f

SYSCLK

System Clock (SYSCLK) Input Frequency

8.33

MHz

t

CS Active to IORD/IOWR Active

10

ns (min)

t

IORD/IOWR Inactive to CS Inactive

10

ns (min)

t

Address Valid to IORD/IOWR Active

30

ns (min)

t

IORD/IOWR Inactive to Address Invalid

10

ns (min)

ISA WRITE TIMING

t

Data Valid to IOWR Active

5

ns (min)

t

IOWR Inactive to Data Invalid

5

ns (min)

t

IOWR Active to Rising Edge of SYSCLK

20

ns (min)

DS100036-4

The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that a Power-on reset does not

occur unintentionally. (See

Section 3.2 ‘Resets’ )

FIGURE 1. ISA Bus Write Timing Diagram

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