5

 2002 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1544

PRELIMINARY

Notes:

(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.

(2) Guaranteed by design.

(3) Applies to S0 only.

(4) Gates 7 and 8 are high whenever 5VSB is present and greater than V

has been tripped.

(5) Applies to S3 sleep state only for 3.3V Dual Memory option. Applies to both S0 and S3 sleep state for 2.5V

Dual Memory Option

(6) Gate 5 is high in S0 and low in the S3 and S5 sleep states.

(7) Gate 6 is high in the S3 sleep state and low in S0 and in the S5 sleep state.

(8) Applies to S3 sleep state and S5 sleep state when the PCI pin is high.

(9) Gate 3 is high in S0 and low in the S3 and S5 sleep states.

(10) Gate 4 is high in the S3 sleep state and the S5 sleep state when the PCI pin is high. Gate 4 is low in S0,

and in the S5 sleep state when the PCI pin is low.

(11) Gate 2 is high in S0 and low in the S3 and S5 sleep states.

(12) Gate 1 is high in the S3 sleep state and the S5 sleep state when the USB pin is high. Gate 1 is low in S0,

and in the S5 sleep state when the USB pin is low.

(13) Applies to S0 only. V

(14) Applies to 2.5V/3.3V Dual Memory, 3.3V Dual and 5V Dual outputs when enabled only. When an output is

disabled, that output is not monitored for OCP. The 1.8V and AGP outputs do not have over current protection.

(15) Minimum and maximum time limits for over current protection to trip when powered up (or enabled) into a

shorted output and when a short is applied to an enabled, OCP protected output.

Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) ± 5%, GND = 0V, V

operating ambient temperature range.

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