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ADE9078 bảng dữ liệu(PDF) 26 Page - Analog Devices

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Data Sheet
ADE9078
Rev. 0 | Page 25 of 107
To select the appropriate capacitance value for the ceramic
capacitors, calculate CL1 and CL2, from the following expression:
CL = ((CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2))/( CL1 + CP1 +
CIN1 + CL2 + CP2 + CIN2)
(1)
Select CL1 and CL2 such that the total capacitance on each clock
pins is equal:
CL1 + CP1 + CIN1 = CL2 + CP2 + CIN2
(2)
Using Equation 1 and Equation 2, the values of CL1 and CL2 can
be calculated.
Load Capacitor Calculation Example
If a crystal with load capacitance specification of 12 pF is selected,
and the measured parasitic capacitances from the PCB traces
are CP1 = CP2 = 2 pF, Equation 1 implies,
CL = ((CL1 + CP1 + CIN1) × (CL2 + CP2 + CIN2))/(CL1 + CP1 +
CIN1 + CL2 + CP2 + CIN2)
12 pF = ((CL1 + 2 pF + 4 pF) × (CL2 + 2 pF + 4 pF))/(CL1 +
2 pF + 4 pF + CL2 + 2 pF + 4 pF)
Assuming CL1 = CL2, to satisfy Equation 2,
12 pF = ((CL1 + 6 pF) × (CL1 + 6 pF))/(CL1 + 6 pF + CL1 + 6 pF)
12 pF = ((CL1 + 6 pF) × (CL1 + 6 pF))/(2 × (CL1 + 6 pF))
12 pF = (CL1 + 6 pF)/2
Thus, CL1 = CL2 = 18 pF.
Based on this example, 18 pF ceramic capacitors are selected for CL1
and CL2. The user must verify the customized values based on care-
ful investigations on multiple devices over the temperature range.
POWER MANAGEMENT
Power Modes
The ADE9078 offers four operating modes: PSM0, PSM1, PSM2,
and PSM3. The entry into the power modes is controlled by the
PM1 and PM0 pins. These pins are checked continuously to
determine which operating mode to enter. Table 8 shows the
PMx pin configurations for each power mode.
Most applications use PSM0 (normal mode). If the user wants
to put the ADE9078 into a low power reset state, use PSM3.
PSM1 and PSM2, in combination with PSM3, enable low power
tamper detection and measurement, which is required in some
regions. These operating modes enable the user to check for a
tamper condition while minimizing power consumption—
because in tamper scenarios, a battery typically powers the
ADE9078.
The current peak detection mode, PSM2, checks if the input
currents are above a user set amplitude. The tamper
measurement mode, PSM1, allows the user to make key
measurements quickly for IRMS, VRMS, active power, and VAR
with a reduced power consumption compared to PSM0.
In the application, the host microcontroller creates a duty cycle
that puts the ADE9078 into PSM2, waits the required time to
receive a result indicated in Table 8, and then returns to PSM3.
This cycle continues once per minute until the tamper checking
cycle ends, which may be up to seven days in some applications. If a
tamper is detected in PSM2, PSM1 is entered and the key measure-
ments are made. After the time required for measurements has
elapsed, the host microcontroller reads the results via the SPI
interface and changes the PM1 and PM0 pins to put the device
back into PSM3. This cycle continues once per minute until the
tamper checking cycle ends, which may be up to seven days in
some applications. Figure 38 shows the functions available in
PSM2 and PSM1.
SINC4
AND
DECIMATION
AVDD
LDO
DVDD
LDO
SPI
1.25V
REFERENCE
TEMP
SENSOR
CF1
TO CF4
IRQ0
IRQ1
SPI
PM1
PM0
ADE9078
PGA
ADC
PGA
ADC
SAR
AVAILABLE IN PSM0
AVAILABLE IN PSM2
DISABLED IN PSM1
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
ADC
METROLOGY FEATURES
(PER PHASE)
IRMS, VRMS
ACTIVE POWER, VA
YX, ANGLE
WAVEFORM BUFFER
ENERGY/POWER/CF
ACCUMULATION
LINE FREQUENCY
ETC.
LOW
POWER
COMPARATOR
Figure 38. Functions Available in PSM1 and PSM2
As indicated in Table 8, the SPI is not available in PSM2. To check
whether the current inputs are above the user configured tamper
threshold, check the IRQ0 and IRQ1 pins (see the Measurements
(PSM2) section for more information).
One register is retained during PSM2 and PSM3: PSM2_CFG, as
shown in Table 8. Note that if PSM0 or PSM1 is entered, PSM2_CFG
returns to it default value and must be rewritten before reentering
PSM2 (see the Measurements (Normal Mode) section,
Measurements (PSM1) section, and Measurements (PSM2)
section for details on functionality in PSM0, PSM1, and PSM2).



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