ADE9078 datasheet(103/108 Pages) AD

103 / 108 page

ADE9078

Data Sheet

Rev. 0 | Page 102 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

CVARSIGN

Phase C reactive power sign bit. The

PWR_SIGN_SEL bit in the EP_CFG selects whether

this feature monitors total or fundamental reactive

power.

0x0

CWSIGN

Phase C active power sign bit.

0x0

BVARSIGN

Phase B reactive power sign bit. The

PWR_SIGN_SEL bit in the EP_CFG selects whether

this feature monitors total or fundamental reactive

power.

0x0

BWSIGN

Phase B active power sign bit.

0x0

AVARSIGN

Phase A reactive power sign bit. The

PWR_SIGN_SEL bit in the EP_CFG selects whether

this feature monitors total or fundamental reactive

power.

0x0

AWSIGN

Phase A active power sign bit.

0x0

0x4A0 WFB_CFG

[15:13] RESERVED

Reserved.

0x0

WF_IN_EN

This setting determines whether the IN waveform

samples are read out of the waveform buffer

through SPI.

0x0

R/W

0 IN waveform samples are not read out of

waveform buffer through SPI.

1 IN waveform samples are read out of waveform

buffer through SPI.

[11:10] RESERVED

Reserved.

0x0

[9:8]

WF_SRC

Waveform buffer source and DREADY, data ready

update rate, selection.

0x0

R/W

00 Sinc4 output, at 16 kSPS.

01 Reserved.

10 Sinc4 + IIR LPF output, at 4 kSPS.

11 Current and voltage channel waveform samples,

processed by the DSP (xI_PCF, xV_PCF) at 4 kSPS.

[7:6]

WF_MODE

Fixed data rate waveforms filling and trigger based

modes.

0x0

R/W

00 Stop when waveform buffer is full.

01 Continuous fill—stop only on enabled trigger

events.

10 Continuous filling—center capture around

enabled trigger events.

11 Continuous fill—save event address of enabled

trigger events.

WF_CAP_SEL

This bit selects whether the waveform buffer is

filled with resampled data or fixed data rate data,

selected in the WF_CAP_SEL bits.

0x0

R/W

0 Resampled data.

1 Fixed data rate data.

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