AD9364BBCZ datasheet(6/33 Pages) AD

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Data Sheet

AD9364

Parameter1

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

Output Voltage

Minimum

0.5

Maximum

VDD_GPO − 0.3

Output Current

DIGITAL SPECIFICATIONS (CMOS)

Logic Inputs

Input Voltage

High

VDD_INTERFACE × 0.8

VDD_INTERFACE

Low

VDD_INTERFACE × 0.2

Input Current

High

−10

+10

μA

Low

−10

+10

μA

Logic Outputs

Output Voltage

High

VDD_INTERFACE × 0.8

Low

VDD_INTERFACE × 0.2

DIGITAL SPECIFICATIONS (LVDS)

Logic Inputs

Input Voltage Range

825

1575

Each differential input in the

pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100

Ω

Logic Outputs

Output Voltage

High

1375

Low

1025

Output Differential Voltage

150

Programmable in 75 mV

steps

Output Offset Voltage

1200

GENERAL-PURPOSE OUTPUTS

Output Voltage

High

VDD_GPO × 0.8

Low

VDD_GPO × 0.2

Output Current

SPI TIMING

VDD_INTERFACE = 1.8 V

SPI_CLK

Period

tCP

Pulse Width

tMP

SPI_ENB Setup to First SPI_CLK

Rising Edge

tSC

Last SPI_CLK Falling Edge to

SPI_ENB Hold

tHC

SPI_DI

Data Input Setup to

SPI_CLK

Data Input Hold to SPI_CLK

SPI_CLK Rising Edge to Output

Data Delay

4-Wire Mode

tCO

3-Wire Mode

tCO

Bus Turnaround Time, Read

tHZM

tCO(max)

After baseband processor

(BBP) drives the last address

bit

Bus Turnaround Time, Read

tHZS

tCO(max)

After the AD9364 drives the

last data bit

Rev. C | Page 5 of 32

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