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MB91F577CSPMC bảng dữ liệu(PDF) 142 Page - Cypress Semiconductor

tên linh kiện MB91F577CSPMC
Giải thích chi tiết về linh kiện  32-bit RISC, load/store architecture, 5-stage pipeline
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MB91F577CSPMC bảng dữ liệu(HTML) 142 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 142 of 163
MB91570 Series
13.4.14 External bus I/F (synchronous mode) timing
(TA: Recommended operating conditions, VCC5 = VCCE = AVCC = 5.0V±10%, VSS = AVSS = 0.0V)
(External load capacitance 50pF)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Max
Cycle time
tCYC
SYSCLK
25
–
ns
ASX delay time
tCHASL,
tCHASH
SYSCLK,
ASX
0.5
18
ns
CS0X to CS3X delay
time
tCHCSL,
tCHCSH
SYSCLK,
CS0X to CS3X
0.5
18
ns
A00 to A21 delay time
tCHAV,
tCHAX
SYSCLK,
A00 to A21
0.5
18
ns
RDX delay time
tCHRL,
tCHRH
SYSCLK,
RDX
0.5
18
ns
RDX minimum pulse
tRLRH
RDX
tCYC×
2 - 20
–
ns
RWT=1, set RWT to 1 or more. *
Data setup
→ RDX ↑
time
tDSRH
RDX,
D16 to D31
18 +
tCYC
–
ns
RWT=1, set RWT to 1 or more. *
RDX
↑→ data hold
tRHDH
0
–
ns
WRnX delay time
tCHWL,
tCHWH
SYSCLK,
WR0X, WR1X
0.5
18
ns
WRnX minimum pulse width
tWLWH
WR0X, WR1X
tCYC - 10
–
ns
WWT=0 *
SYSCLK
↑→
data output time
tCHDV
SYSCLK,
D16 to D31
0.5
18
ns
SYSCLK
↑→ data
hold time
tCHDX
–
18
ns
Set WRCS to 1 or more.
SYSCLK
↑→ address output
time
tCHMAV
SYSCLK,
D16 to D31
0.5
18
ns
SYSCLK
↑→ address hold time t
CHMAX
–
18
ns
In multiplex mode, set as follows:
Set CSWR and CSRD to 2 or more.
ASCY must satisfy the following
conditions because of setting
ADCY>ASCY and protocol violation
prevention.
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
Refer to Hardware Manual for details.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated
value.



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