MB91F577CSPMC datasheet(137/163 Pages) CYPRESS

tên linh kiện	MB91F577CSPMC

Giải thích chi tiết về linh kiện	32-bit RISC, load/store architecture, 5-stage pipeline

PDF	163 Pages

Scroll/Zoom	100%

nhà sản xuất	CYPRESS [Cypress Semiconductor]

Trang chủ	http://www.cypress.com

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137 / 163 page

Document Number: 002-04725 Rev.*A

Page 137 of 163

MB91570 Series

Bit setting: ESCR: SCES = 1, ECCR: SCDE = 1

(TA: Recommended operating conditions, VCC5 = 5.0V±10%, VCCE = 5.0V±10%, VSS = AVSS = 0.0V)

Parameter

Symbol

Pin name

Conditions

Value

Unit

Remarks

Min

Max

Serial clock cycle time

tSCYC

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7

–

5tCPP

–

Internal shift clock

Mode:

CL=80pF+1 • TTL

SCK

↓→

SOT delay time

tSLOVI

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7,

SOT2,SOT3,

SOT4,SOT5,

SOT6,SOT7

-50

+50

Valid SIN

→

SCK

↑ setup time

tIVSHI

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7,

SIN2,SIN3,

SIN4,SIN5,

SIN6,SIN7

tCPP+80

–

SCK

↑→

Valid SIN hold time

tSHIXI

–

SOT

→

SCK

↑ delay time

tSOVHI

SCK2,SCK3,

SCK4,SCK5,

SCK6,SCK7,

SOT2,SOT3,

SOT4,SOT5,

SOT6,SOT7

3tCPP-70

–

Notes:

• CL is the load capacitance applied to pins during testing.

• The maximum baud rate is limited by the internal operation clock used and other parameters.

Refer to Hardware Manual for details.

Internal shift clock mode

2.4V

0.8V

SINx

SOTx

SCKx

SCYC

SHIXI

IVSHI

VIL

VIH

2.4V

0.8V

SLOVI

SOVHI

2.4V

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