HMC7043

Data Sheet

Rev. B | Page 38 of 43

SYSREF Status Register (Register 0x0091)

Table 39. SYSREF Status

Address

Bits

Bit Name

Settings

Description

Access

0x0091

[7:5]

Reserved

Reserved.

R

4

Channel outputs

FSM busy

One of clock outputs FSM requested clock, and it is running.

[3:0]

SYSREF FSM

State[3:0]

Indicates the current step of the SYSREF reseed process. Note that the three

different progressions are caused by different trigger events (reseed, pulse

generator, reserved).

0000

Reset.

0010

Done.

0100

Get ready.

0101

Get ready.

0110

Get ready.

1010

Running (pulse generator).

1011

Start.

1100

Power up.

1101

Power up.

1110

Power up.

1111

Clear reset.

Bias Settings (Register 0x0096 to Register 0x00B8)

For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.

Table 40. Reserved Registers

Address

Bits

Bit Name

Settings

Description

Access

0x0098

[7:0]

Reserved

Reserved

RW

0x0099

[7:0]

Reserved

Reserved

RW

0x009D

[7:0]

Reserved

Reserved

RW

0x009E

[7:0]

Reserved

Reserved

RW

0x009F

[7:0]

Reserved

Clock output driver low power setting (set to 0x4D instead of default value)

RW

0x00A0

[7:0]

Reserved

Clock output driver high power setting (set to 0xDF instead of default value)

RW

0x00A2

[7:0]

Reserved

Reserved

RW

0x00A3

[7:0]

Reserved

Reserved

RW

0x00A4

[7:0]

Reserved

Reserved

RW

0x00AD

[7:0]

Reserved

Reserved

RW

0x00B5

[7:0]

Reserved

Reserved

RW

0x00B6

[7:0]

Reserved

Reserved

RW

0x00B7

[7:0]

Reserved

Reserved

RW

0x00B8

[7:0]

Reserved

Reserved

RW