HMC701LP6CE datasheet(28/40 Pages) AD

28 / 40 page

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Phone: 978-250-3343

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HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

a typical rEaD cycle is shown in Figure 20.

a. the Master (host) asserts both SEn (Serial Port Enable) and SDi to indicate a rEaD

cycle, followed by a rising edge ScLK

b. the slave (synthesizer) reads SDi on the 1st rising edge of ScLK after SEn. SDi high initiates

the rEaD cycle (rD)

c. Host places the six address bits on the next six falling edges of ScLK, MSB first.

d. Slave registers the address bits on the next six rising edges of ScLK (2-7).

e. Slave places the 24 data bits on the next 24 rising edges of ScK (8-31), MSB first .

f. Host registers the data bits on the next 24 falling edges of ScK (8-31).

g. SEn is de-asserted on or after the 32nd falling edge of ScLK.

h. the 32nd falling edge of ScLK completes the cycle

Figure 20. Serial Port Timing Diagram - READ

Reg 00h Chip ID (Read Only) Register

Bit

Type

Name

Width

Default

Description

[23:0]

chip iD

581502h

chip iD

Table 11. Reg 00h Strobe (Write Only) Register

Bit

Type

Name

Width

Default

Description

Str

global_swrst_regs

Strobe to soft reset the SPi registers

Str

global_swrst_dig

Strobe to soft reset the rest of digital

Str

mcnt_resynch

reserved

Str

tsens_spi_strobe

Strobe to clock the temp measurement on

demand

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