4

Integrated

Circuit

Systems, Inc.

ICS950910

0735A—03/18/04

Pin Description (Continued)

PIN

PIN

PIN

#

NAME

TYPE

29

DDRC5

OUT

"Complimentary" Clock of differential pair output.

30

DDRT5

OUT

"True" Clock of differential pair output.

31

DDRC4

OUT

"Complimentary" Clock of differential pair output.

32

DDRT4

OUT

"True" Clock of differential pair output.

33

GND

PWR

Ground pin.

34

VDD2.5

PWR

Power supply, nominal 2.5V

35

DDRC3

OUT

"Complimentary" Clock of differential pair output.

36

DDRT3

OUT

"True" Clock of differential pair output.

37

DDRC2

OUT

"Complimentary" Clock of differential pair output.

38

DDRT2

OUT

"True" Clock of differential pair output.

39

GND

PWR

Ground pin.

40

VDD2.5

PWR

Power supply, nominal 2.5V

41

DDRC1

OUT

"Complimentary" Clock of differential pair output.

42

DDRT1

OUT

"True" Clock of differential pair output.

43

DDRC0

OUT

"Complimentary" Clock of differential pair output.

44

DDRT0

OUT

"True" Clock of differential pair output.

45

BUF_IN

IN

Input Buffers for memory outputs.

46

FBOUT

OUT

Memory feed back output.

47

GND

PWR

Ground pin.

48

CPUT_CS

OUT

True clock of differential pair 2.5V push-pull CPU outputs.

49

CPUC_CS

OUT

Complimentary" clocks of differential pair 2.5V push-pull CPU outputs.

50

VDDCPU2.5

PWR

Power pin for the CPUCLKs. 2.5V

51

VDDCPU3.3

PWR

Power pin for the CPUCLKs. 3.3V

52

CPUCLKC/CPUCLKODC

OUT

"Complementary" clocks of differential pair CPU outputs. These are current mode

outputs. External resistors are required for voltage bias / "Complementary" clocks of

differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /

2.5V CPU clock output.

53

CPUCLKT/CPUCLKODT

OUT

"True" clocks of differential pair CPU outputs. These are current mode outputs.

External resistors are required for voltage bias / "True" clocks of differential pair CPU

outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock

output.

54

GND

PWR

Ground pin.

55

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

56

Vtt_PWRGD#**/REF1

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active low input. / 14.318 MHz

reference clock.

DESCRIPTION