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CDCP1803 bảng dữ liệu(PDF) 1 Page - Texas Instruments

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tên linh kiện CDCP1803
Giải thích chi tiết về linh kiện  1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
PDF  19 Pages
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CDCP1803 bảng dữ liệu(HTML) 1 Page - Texas Instruments

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CDCP1803
1:3 LVPECL CLOCK BUFFER
WITH PROGRAMMABLE DIVIDER
SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D Distributes One Differential Clock Input to
Three LVPECL Differential Clock Outputs
D Programmable Output Divider for Two
LVPECL Outputs
D Low-Output Skew 15 ps (Typical)
D VCC Range 3 V−3.6 V
D Signaling Rate Up to 800-MHz LVPECL
D Differential Input Stage for Wide
Common-Mode Range
D Provides VBB Bias Voltage Output for
Single-Ended Input Signals
D Receiver Input Threshold +75 mV
D 24-Pin MLF Package (4 mm x 4 mm)
D Accepts Any Differential Signaling: LVDS,
HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
description
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential
clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCP1803 is specifically
designed for driving 50-
Ω transmission lines.
The CDCP1803 has three control pins, S0, S1, and S2, to select different output mode settings, see Table 1
for details. The CDCP1803 is characterized for operation from −40
°C to 85°C. For use in single-ended driver
applications, the CDCP1803 also provides a VBB output pin that can be directly connected to the unused input
as a common-mode voltage reference.
Copyright
 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
MLF PACKAGE
(TOP VIEW)
1
2
3
4
6
5
18
17
13
14
15
16
EN
IN
VBB
S0
Y1
Vdd1
VddPECL
VddPECL
Vdd1
Y1
IN
VSS{
{ PowerPad must be connected to V
SS.
VSS


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