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C1004 bảng dữ liệu(PDF) 2 Page - IMP, Inc |
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C1004 bảng dữ liệu(HTML) 2 Page - IMP, Inc |
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2 / 2 page ![]() 18 C1004-4-98 Physical Characteristics VGS = 5.0V VGS = 4.0V VGS = 3.0V VGS = 2.0V VGS = 1.0V 0 5.0 35.0 28.0 21.0 14.0 1.0 2.0 3.0 4.0 ID vs VD, W/L = 20/1.2 N-ch Transistor IV Characteristics of a 20/1.2 device 7.0 0 Drain Voltage (V) V DS VGS = –5.0V VGS = –4.0V VGS = –3.0V VGS = –2.0V 0 –5.0 –15.0 –12.0 –9.0 –6.0 –1.0 –2.0 –3.0 –4.0 ID vs VD, W/L = 20/1.2 P-ch Transistor IV Characteristics of a 20/1.2 device –3.0 0 Drain Voltage (V) V DS Starting Material P <100> N+/P+ Width/Space 2.0 / 1.2 µm Starting Mat. Resistivity 7-8.5 Ω-cm N+ To P+ Space 7.0 µm Typ. Operating Voltage 5V Contact To Poly Space 0.8 µm Well Type N-well Contact Overlap Of Diffusion 0.7 µm Metal Layers 2 Contact Overlap Of Poly 0.7 µm Poly Layers 1 Metal-1 Overlap Of Contact 0.7 µm Contact Size 1.2x1.2 µm Metal-1 Overlap Of Via 0.7 µm Via Size 1.2x1.2 µm Metal-2 Overlap Of Via 0.7 µm Metal-1 Width/Space 1.4 / 1.2 µm Minimum Pad Opening 65x65 µm Metal-2 Width/Space 2.0 / 1.4 µm Minimum Pad-to-Pad Spacing 5.0 µm Gate Poly Width/Space 1.0 / 1.4 µm Minimum Pad Pitch 80.0 µm Metal 2 Metal 1 SIO2 LTO n+ n+ p n+ p+ p Field Oxide N-well p+ substrate p–epi p+ p+ LTO Process C1004 |
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