LM6218N datasheet(7/13 Pages) NSC

7 / 13 page

Application Information (Continued)

Examples of unity gain connections for a voltage follower, In-

verter, and integrator driving capacitive loads up to 1000 pF

are shown here. Different R1–C1 time constants and capaci-

tive loads will have an effect on settling times.

Input Bias Current Compensation

Input bias current of the first op amp can be reduced or bal-

anced out by the second op amp. Both amplifiers are laid out

in mirror image fashion and in close proximity to each other,

thus both input bias currents will be nearly identical and will

track with temperature. With both op amp inputs at the same

potential, a second op amp can be used to convert bias cur-

rent to voltage, and then back to current feeding the first op

amp using large value resistors to reduce the bias current to

the level of the offset current.

Examples are shown here for an inverting application, (a)

where the inputs are at ground potential, and a second cir-

cuit (b) for compensating bias currents for both inputs.

Voltage Follower

DS010254-10

For CL = 1000 pF, Small signal BW = 5 MHz

20 Vp-p BW = 500 kHz

Inverter

DS010254-11

Settling time to 0.01%, 10V Step

For CL = 1000 pF, settling time ≈ 1500 ns

For CL = 300 pF, settling time ≈ 500 ns

Integrator

DS010254-12

LM6218N bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI)