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UU97950G-P48-R bảng dữ liệu(PDF) 7 Page - Unisonic Technologies |
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UU97950G-P48-R bảng dữ liệu(HTML) 7 Page - Unisonic Technologies |
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7 / 14 page ![]() UU97950 Advance CMOS IC UNISONICTECHNOLOGIESCO.,LTD 7 of 14 www.unisonic.com.tw QW-R125-048.a FUNCTION DESCRIPTIONS (Cont.) Read Command Register and Transfer Method The Command Registers can be read during read mode. The sequence for the command register read is shown below. S 0 1 1 1 1 1 0 A 1 ADSET A Slave address R/W Command 0 S 0 1 1 1 1 1 0 R/W 1 A Data A P Slave address The command register addresses are described in 6. Command Description (ADSET command). The following register settings can be read in this mode. Register D7 D6 D5 D4 D3 D2 D1 D0 Address REG1 0 0 P5 P4 P3 P2 P1 P0 23h REG2 P7 P6 P5 P4 P3 P2 P1 P0 24h REG1: P5= Software reset condition P4 to P0 = EVR setting REG2: P7 to P6 = Frame Frequency (FR) setting P5 to P4 = Power Save Mode (SR) setting P3 = LCD drive waveform setting P2 = Display ON/ OFF setting P1= APON setting P0 = APOFF setting LCD Driver Bias Circuit This device generates LCD driving voltage with on-chip Buffer AMP And it can drive LCD at low power consumption. Line and frame inversion set in DISCTL command. Refer to the LCD driving waveform about each LCD diving waveform Reset initialize condition Initial condition after execute Software Reset is as follows. Display OFF. DDRAM address is initialized Refer to Command Description about initialize value of register. COMMAND / FUCTION LIST Description List of Command / Function Command Function 1 Address set(ADSET) DDRAM address setting(00-22h) 2 EVR set (EVRSET) EVR setting(0-31) 3 Display Control(DISCTL) Frame Frequency, Power save mode setting 4 IC operation set (ICSET) LCD drive mode,software reset, display on/off 5 All pixel Control(APCTL) All pixel control during display ON |
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