82801AB datasheet(56/414 Pages) INTEL

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Functional Description

5-6

82801AA and 82801AB Datasheet

5.2.1.3

Cycle Type / Direction (CYCTYPE + DIR)

The ICH always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive

bit 0 to 0. Table 5-3 shows the valid bit encodings:

5.2.1.4

SIZE

Bits[3:2] are reserved. The ICH always drives them to 00. Peripherals running bus master cycles

are also supposed to drive 00 for bits 3:2; however, the ICH ignores those bits. Bits[1:0] are

encoded as shown in Table 5-4.

5.2.1.5

SYNC

Valid values for the SYNC field are shown in Table 5-5.

NOTE: All other combinations are RESERVED.

Table 5-3. Cycle Type Bit Definitions

Bits[3:2]

Bit[1]

Definition

I/O Read

I/O Write

Memory Read

Memory Write

DMA Read

DMA Write

Reserved. If a peripheral performing a bus master cycle generates this value, the

ICH aborts the cycle.

Table 5-4. Transfer Size Bit Definition

Bits[1:0]

Size

8 bit transfer (1 byte)

16-bit transfer (2 bytes)

Reserved. The ICH never drives this combination. If a peripheral running a bus master cycle

drives this combination, the ICH may abort the transfer.

32 bit transfer (4 bytes)

Table 5-5. SYNC Bit Definition

Bits[3:0]

Indication

0000

Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request

deassertion and no more transfers desired for that channel.

0101

Short Wait: Part indicating wait states. For bus master cycles, the ICH does not use this

encoding. It, instead, uses the Long Wait encoding (see next encoding below).

0110

Long Wait: Part indicating wait states, and many wait states will be added. This encoding

driven by the ICH for bus master cycles, rather than the Short Wait (0101).

1001

Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and

more DMA transfers desired to continue after this transfer. This value is valid only on DMA

transfers and is not allowed for any other type of cycle.

1010

Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#

signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious

error in this transfer. For DMA transfers, this not only indicates an error, but also indicates

DMA request deassertion and no more transfers desired for that channel.

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