AT49LW080 datasheet(10/34 Pages) ATMEL

10 / 34 page

AT49LW080/040

1966C–FLASH–03/02

WRITE: Write operations consist of preamble, data, TAR and SYNC fields as shown in

Figure 3 and described in Table 6.

WRITE CYCLES, SINGLE BYTE: All devices that support FWH Memory Write cycles

must support single-byte writes. FWH Memory Write cycles use the same preamble as

FWH Memory Read cycles.

For write cycles, after the preamble, the master writes the low nibble, then the high nib-

ble of data. After that the master drives a TAR field to give ownership of the bus to the

FWH. After the second clock of the TAR phase, the target device assumes the bus and

begins driving SYNC values. A TAR field to give control back to the master follows this.

Figure 3. FWH Single-byte Write Waveforms

Note:

1. Field contents are valid on the rising edge of the present clock cycle.

IDSEL

MADDR

MSIZE

TAR

SYNC

CLK

FWH4

FWH[3:0]

DATA

PREAMBLE

START

Table 6. FWH Write Cycle

Clock Cycle

Field Name

Field

Contents

(1)

FWH[3:0]

Direction

Comments

START

1110b

FWH4 must be active (low) for the part to respond. Only the last

start field (before FWH4 transitioning high) should be recognized.

The START field contents indicate an FWH memory write cycle.

IDSEL

0000b

1111b

Indicates which FWH device should respond. If the IDSEL (ID

select) field matches the value ID[3:0], then that particular device

will respond to subsequent commands.

3 - 9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory address.

YYYY is one nibble of the entire address. Addresses are

transferred most significant nibble first.

MSIZE

0000b (1 byte)

The FWH only supports single-byte writes.

DATA

YYYY

This field is the least significant nibble of the data byte. This data

is either the data to be programmed into the Flash memory or

any valid Flash command.

DATA

YYYY

This field is the most significant nibble of the data byte.

TAR0

1111b

then float

In this clock cycle, the master (ICH) has driven the bus to all 1s

and then floats the bus prior to the next clock cycle. This is the

firstpartofthe bus “turnaround cycle”.

TAR1

1111b (float)

Float then

OUT

The FWH takes control of the bus during this cycle. During the

next clock cycle it will be driving the “sync” data.

RSYNC

0000b

OUT

The FWH outputs the values 0000, indicating that it has received

data or a Flash command.

TAR0

1111b

OUT

then Float

The FWH Flash memory drives FWH0 - FWH 3 to 1111b to

indicate a turnaround cycle.

TAR1

1111b (float)

Float then

The FWH Flash memory floats its outputs, the master (ICH)

takes control of FWH3 - FWH0.

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