Data Sheet

ADGS1412

Rev. 0 | Page 23 of 25

REGISTER DETAILS

SWITCH DATA REGISTER

Address: 0x01, Reset: 0x00, Name: SW_DATA

The switch data register controls the status of the four switches of the ADGS1412.

Table 12. Bit Descriptions for SW_DATA

Bits

Bit Name

Settings

Description

Default

Access

[7:4]

Reserved

These bits are reserved; set these bits to 0.

0x0

R

3

SW4_EN

Enable bit for SW4.

0x0

R/W

0

SW4 open.

1

SW4 closed.

2

SW3_EN

Enable bit for SW3.

0x0

R/W

0

SW3 open.

1

SW3 closed.

1

SW2_EN

Enable bit for SW2.

0x0

R/W

0

SW2 open.

1

SW2 closed.

0

SW1_EN

Enable bit for SW1.

0x0

R/W

0

SW1 open.

1

SW1 closed.

ERROR CONFIGURATION REGISTER

Address: 0x02, Reset: 0x06, Name: ERR_CONFIG

The error configuration register allows the user to enable and disable the relevant error features as required.

Table 13. Bit Descriptions for ERR_CONFIG

Bits

Bit Name

Settings

Description

Default

Access

[7:3]

Reserved

These bits are reserved; set these bits to 0.

0x0

R

2

RW_ERR_EN

Enable bit for detecting invalid read/write address.

0x1

R/W

0

Disabled.

1

Enabled.

1

SCLK_ERR_EN

Enable bit for detecting the correct number of SCLK cycles in a SPI frame.

16 SCLK cycles are expected when CRC is disabled and burst mode is

disabled. 24 SCLK cycles are expected when CRC is enabled and burst

mode is disabled. A multiple of 16 SCLK cycles are expected when CRC is

disabled and burst mode is enabled. A multiple of 24 SCLK cycles are

expected when CRC is enabled and burst mode is enabled.

0x1

R/W

0

Disabled.

1

Enabled.

0

CRC_ERR_EN

Enable bit for CRC error detection. SPI frames are 24 bits wide when

enabled.

0x0

R/W

0

Disabled.

1

Enabled.