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HD3SS460

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SLLSEM7D – JANUARY 2015 – REVISED JANUARY 2017

Product Folder Links: HD3SS460

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Copyright © 2015–2017, Texas Instruments Incorporated

Layout Guidelines (continued)

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Decoupling capacitors should be placed next to each power terminal on the HD3SS460. Care should be

taken to minimize the stub length of the trace connecting the capacitor to the power pin.

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Avoid sharing vias between multiple decoupling capacitors.

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Place vias as close as possible to the decoupling capacitor solder pad.

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Widen VCC/GND planes to reduce effect of static and dynamic IR drop.

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The VBUS traces/planes must be wide enough to carry maximum of 2 A current.

11.2 Layout Example

Figure 20, Figure 21, and Figure 22 illustrate some guidelines for layout. Actual layout should be optimized for

various factors such as board geometry, connector type, and application.

Figure 20. USB Type C Connector to HD3SS460 Signal Routing

Figure 21. Dual SMT Mid-Mount Type C Connector Layout Example Zoom-in