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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TMS320C51 bảng dữ liệu(PDF) 73 Page - Texas Instruments |
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TMS320C51 bảng dữ liệu(HTML) 73 Page - Texas Instruments |
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73 / 87 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 73 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SERIAL-PORT TRANSMIT TIMING IN TDM MODE switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26) PARAMETER ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX th(TCH-TDV) Hold time, TDAT/TADD valid after TCLK rising edge 0 0 0 ns td(TCH-TFV) Delay time, TFRM valid after TCLK rising edge† H 3H + 10 H 3H + 7 3H + 5 ns td(TC-TDV) Delay time, TCLK to valid TDAT/TADD 20 15 12 ns † TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is illustrated in the receive timing diagram in Figure 27. timing requirements over recommended ranges of supply voltage and operating ambient-air temperature [H = 0.5tc(CO)] (see Figure 26) ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX tc(SCK) Cycle time, serial-port clock 5.2H‡ 8H§ ¶ 5.2H‡ 8H§ ¶ 5.2H‡ 8H§ ¶ ns tf(SCK) Fall time, serial-port clock 8# 6# 5# ns tr(SCK) Rise time, serial-port clock 8# 6# 5# ns tw(SCK) Pulse duration, serial-port clock low/ high 2.1H‡ 2.1H‡ 2.1H‡ ns ‡ Values ensured by design and are not tested § When SCK is generated internally ¶ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of 0 Hz but tested as a much higher frequency to minimize test time. # Values derived from characterization data and not tested A7 B2 B8 B7 A3 B12 A2 A0 A1 B0 B1 B13 B14 B0 tw(SCK) tw(SCK) td(TC-TDV) th(TCH-TDV) tr(SCK) tf(SCK) td(TCH-TFV) TFRM TADD TDAT TCLK B15 tc(SCK) td(TC-TDV) th(TCH-TDV) td(TCH-TFV) Figure 26. Serial-Port Transmit Timing in TDM Mode |
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