TMS28F210 datasheet(12/25 Pages) TI

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Write Erase-Verify Command

Setup

Last

Address?

Start

Increment

Address

Read

and Verify

Word

X = X + 1

Wait = 10 ms

Pass

Write Read Command

X = 1000?

Interactive

Mode

Program All

Words to

0000h

Apply VPPL

Power

Down

Apply VPPL

Address = 00h

VCC = 5 V ± 10%, VPP = 12 V ± 5%

X = 1

Device Passed

Device Failed

Yes

Fail

Yes

Wait = 6

µs

Preprogram

All

Words =

0000h

Write Set-Up-Erase Command

Write Erase Command

TMS28F210

65536 BY 16-BIT

FLASH MEMORY

SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Bus

Operation

Command

Comments

Entire memory must = 0000h

before erasure

Use Fastwrite

programming algorithm

Initialize addresses

Standby

Wait for VPP to ramp to

VPPH (see Note A)

Initialize pulse count

Write

Set-Up-

Erase

Data = 0020h

Write

Erase

Data = 0020h

Standby

Wait = 10 ms

Write

Erase

Verify

Addr = Word to verify;

data = 00A0h; ends the erase

operation

Standby

Wait = 6

µs

Read

Read word to verify erasure;

compare output to FFFFh

Write

Read

Data = 0000h; resets register

for read operations

Standby

Wait for VPP to ramp to

VPPL (see Note B)

NOTES: A. Refer to the recommended operating conditions for the value of VPPH

B. Refer to the recommended operating conditions for the value of VPPL

Figure 2. Flash-Erase Flowchart: Fasterase Algorithm

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