PERICOMPI7C8150 datasheet(13/106 Pages) PERICOM

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PI7C8150

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

August 22, 2002 – Revision 1.02

Name

Pin #

Type

Description

P_IRDY_L

STS

Primary IRDY (Active LOW). Driven by the initiator

of a transaction to indicate its ability to complete current

data phase on the primary side. Once asserted in a data

phase, it is not de-asserted until the end of the data

phase. Before tri-stated, it is driven to a de-asserted state

for one cycle.

P_TRDY_L

STS

Primary TRDY (Active LOW). Driven by the target of

a transaction to indicate its ability to complete current

data phase on the primary side. Once asserted in a data

phase, it is not de-asserted until the end of the data

phase. Before tri-stated,

it is driven to a de-asserted state for one cycle.

P_DEVSEL_L

STS

Primary Device Select (Active LOW). Asserted by the

target indicating that the device is accepting the

transaction. As a master, PI7C8150 waits for the

assertion of this signal within 5 cycles of P_FRAME_L

assertion; otherwise, terminate with master abort. Before

tri-stated, it is driven to a

de-asserted state for one cycle.

P_STOP_L

STS

Primary STOP (Active LOW). Asserted by the target

indicating that the target is requesting the initiator to stop

the current transaction. Before tri-stated, it is driven to a

de-asserted state for one cycle.

P_LOCK_L

STS

Primary LOCK (Active LOW). Asserted by the

master for multiple transactions to complete.

P_IDSEL

Primary ID Select. Used as a chip select line for Type

0 configuration access to PI7C8150 configuration space.

P_PERR_L

STS

Primary Parity Error (Active LOW). Asserted when

a data parity error is detected for data received on the

primary interface. Before being tri-stated, it is driven to

a de-asserted state for one cycle.

P_SERR_L

Primary System Error (Active LOW). Can be driven

LOW by any device to indicate a system error condition.

PI7C8150 drives this pin on:

Address parity error

Posted write data parity error on target bus

Secondary S_SERR_L asserted

Master abort during posted write transaction

Target abort during posted write transaction

Posted write transaction discarded

Delayed write request discarded

Delayed read request discarded

Delayed transaction master timeout

This signal requires an external pull-up resistor for

proper operation.

P_REQ_L

Primary Request (Active LOW): This is asserted by

PI7C8150 to indicate that it wants to start a transaction

on the primary bus. PI7C8150 de-asserts this pin for at

least 2 PCI clock cycles before asserting it again.

P_GNT_L

Primary Grant (Active LOW): When asserted,

PI7C8150 can access the primary bus. During idle and

P_GNT_L asserted, PI7C8150 will drive P_AD, P_CBE,

and P_PAR to valid logic levels.

P_RESET_L

Primary RESET (Active LOW): When P_RESET_L is

active, all PCI signals should be asynchronously tri-

stated.

P_M66EN

102

Primary Interface 66MHz Operation.

This input is used to specify if PI7C8150 is capable of

running at 66MHz. For 66MHz operation on the Primary

bus, this signal should be pulled “HIGH”. For 33MHz

operation on the Primary bus, this signal should be

pulled “LOW”. In this condition, S_M66EN will need

to be “LOW”, forcing the secondary buse to run at

33MHz also.

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