Pin Description

Pin

Pin Name

Pin Function

1

Vcc5V

Supply Voltage Input (5V nominal)

2

Divsel

Selects Phase Mode. Logic low selects 4 phase. Logic high selects 3 phase. 2 phase

operation is achieved by using 2 outputs in 4 phase mode.

3

Clksel

Clock Select: Logic high selects internal clock. Logic low selects external clock.

4

Extclk

External Clock Input. Output frequency = Clock Input / No. of Phases. Connect to Vcc5V to

select internal clock.

5

Rref

Connects to external reference resistor. Sets the operating frequency of the internal clock

and the ramp time for the PWM. Reference voltage at this pin is 1.26V.

6

Vid0

5-Bit DAC Input (LSB).

7

Vid1

5-Bit DAC Input.

8

Vid2

5-Bit DAC Input.

9

Vid3

5-Bit DAC Input.

10

Vid4

5-Bit DAC Input (MSB)

11

OC+

Over-current Comparator. Non-inverting input.

12

OC−

Over-current Comparator. Inverting input.

13

COMP

Compensation Pin. This is the output of the internal transconductance amplifier.

Compensation network should be connected between this pin and feedback ground FBG.

14

FB

Feedback Input. Normally Kelvin connected to supply output.

15

Bgout

Current Limit Flag. Goes to logic low when current limit is activated. When over-current

condition is removed, this pin is weakly pulled up to Vcc5V.

16

FBG

Feedback Ground. This pin should be connected to the ground at the supply output.

17

ENABLE

Output Enable Pin. Tie to logic high to enable and logic low to disable.

18

GND

Power Ground Pin.

19

DRV2

Phase 2 Output.

20

DRV0

Phase 0 Output.

21

Vcc12V

Supply Voltage for FET Drivers DRV0:3.

22

DRV1

Phase 1 Output.

23

DRV3

Phase 3 Output.

24

PWRGD

Power Good. This is an open-drain output that goes low (low impedance to ground) when

the output voltage travels out of the threshold window, and resume to open-drain state when

V

≤ V

according to VID code. Connect a 1nF capacitor to ground to filter out the switching noise

coupling from DRV3 to this pin.

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