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STW4510 bảng dữ liệu(PDF) 18 Page - STMicroelectronics |
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STW4510 bảng dữ liệu(HTML) 18 Page - STMicroelectronics |
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18 / 57 page ![]() Obsolete Product(s) - Obsolete Product(s) Functional description STw4510 18/57 In this present version, Vdig is ON at start-up and Vana(i) are switched OFF. For more information, please contact STMicroelectronics sales office. 3.2.6 Device reset by processor Sw_resetn In the event of a reset from processor to STw4510, Sw_resetn signal set to “0”, the device resets all control registers, except registers at address 1Eh, 1Fh and 03h. As a consequence, after a Sw_reset, Vmmc is switched OFF, all Vana(i) (i=1 to 3) and Vdig are set to their start-up default value (ON or OFF). When a low level is applied on Pon signal, all registers are reset at their initial value and Pon signal goes back to “1”. 3.2.7 I2C interface The I2C interface controls power management and all programmable functions. I2C is configured as slave serial interface compatible with I2C registered trademark of Phillips Inc. (version 2.1). I2C interface description STw4510 I2C is a slave serial interface with a serial data line (SDA) and a serial clock line (SCL) SCL: input clock used to shift data SDA: input/output bidirectional data transfers It is composed of: On filter to reject spikes on the bus data line and preserve data integrity Bidirectional data transfers up to 400kbit/s (Fast-mode) via SDA signal The SDA signal contains the input/output control and data signals that are shifted in the device, MSB first. The first bit must be high (START) followed by the Device ID (7 bits) and Read/Write bit control (1 indicates read access, a logical 0 indicates a write access). Device ID: Device ID in write mode: 5Ch (01011100) Device ID in read mode: 5Dh (01011101) STw4510 then sends an acknowledge at the end of an 8 bit transfer. The following 8-bits correspond to the register address followed by another acknowledge. The 8-bit data field is sent last and is also followed by a last acknowledge. Table 7. Device ID b7 b6 b5 b4 b3 b2 b1 b0 AdrID6 AdrID5 AdrID4 AdrID3 AdrID2 AdrID1 AdrID0 R/W Table 8. Register address b7 b6 b5 b4 b3 b2 b1 b0 RegADR7 RegADR6 RegADR5 RegADR4 RegADR3 RegADR2 RegADR1 RegADR0 |
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