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PS8315-2

04/08/99

PI6C103

Precision Clock Synthesizer for Mobile PCs

Notes:

1. All timing is referenced to the CPUCLK.

2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.

3 Internal means inside the chip.

4. All other clocks continiue to run undisturbed.

5. PWR_DWN# CPU_STOP# are shown in a high state.

6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.

PCI_STOP# is an input signal used to turn off PCI clocks for low

power operation. PCI clocks are stopped in the low state and started

PCI_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.

4. The Shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.

PWR_DWN#TimingDiagram

The PWR_DWN# is used to place the device in a very low power

state. PWR_DWN# is an asynchronous active low input. Internal

clocks are stopped after the device is put in power-down mode.

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

(Free-running)

CPU_STOP#

PCI_STOP#

PWR_DWN#

PCICLK

(External)

CPUCLK

(Internal)

PCICLK

(Internal)

VCO

PWR_DWN#

CPUCLK

(External)

PCICLK

(External)

Crystal

with a guaranteed full high pulse width. There is ONLY one rising

edge of external PCICLK after the clock control logic.

The power-on latency is less than 3ms. PCI_STOP# and

CPU_STOP# are “don’t cares” during the power-down operations.

The REF clock is stopped in the LOW state as soon as possible.