74ALVC02D datasheet(2/13 Pages) PHILIPS

2 / 13 page

2003 Jul 14

Philips Semiconductors

Product speciﬁcation

Quad 2-input NOR gate

74ALVC02

FEATURES

• Wide supply voltage range from 1.65 to 3.6 V

• 3.6 V tolerant inputs/outputs

• CMOS low power consumption

• Direct interface with TTL levels (2.7 to 3.6 V)

• Power-down mode

• Latch-up performance exceeds 250 mA

• Complies with JEDEC standard:

JESD8-7 (1.65 to 1.95 V)

JESD8-5 (2.3 to 2.7 V)

JESD8B/JESD36 (2.7 to 3.6 V).

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

DESCRIPTION

The 74ALVC02 is a high-performance, low-power,

low-voltage, Si-gate CMOS device and superior to most

advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit

tolerant for slower input rise and fall times.

The 74ALVC02 provides the 2-input NOR function.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay nA, nB to nY

VCC = 1.8 V; CL = 30 pF; RL =1kΩ

2.8

VCC = 2.5 V; CL = 30 pF; RL = 500 Ω

2.0

VCC = 2.7 V; CL = 50 pF; RL = 500 Ω

2.5

VCC = 3.3 V; CL = 50 pF; RL = 500 Ω

2.2

input capacitance

3.5

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

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