LAN9116 datasheet(13/109 Pages) MICROCHIP

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 2005-2016 Microchip Technology Inc.

DS00002268A-page 13

LAN9116

Note 2-1

Please refer to the Microchip application note AN 12.5 titled “Designing with the LAN9118 - Getting

Started”. It is also important to note that this application note applies to the whole Microchip LAN9118

family of Ethernet controllers. However, subtle differences may apply.

2.1

Buffer Types

1,66

Core Ground

GND_CORE

Ground for internal digital logic

PLL Power

VDD_PLL

1.8V Power from the internal PLL

regulator. This external pin must be

connected to a 10uF 0.1-Ohm ESR

capacitor, in parallel with a 0.01uF

capacitor to Ground. This pin must not

be used to supply power to other

external devices. See Note 2-1

PLL Ground

VSS_PLL

GND for the PLL

Reference Power

VDD_REF

Connected to 3.3v power and used as

the reference voltage for the internal

PLL

Reference Ground

VSS_REF

Ground for internal PLL reference

voltage

TABLE 2-6:

BUFFER TYPES

Type

Description

Input pin

Schmitt triggered Input

O12

Output with 12mA sink and 12mA source

OD12

Open-drain output with 12mA sink

IO8

I/O with 8mA symmetrical drive

OD8

Open-drain output with 8mA sink

Output 8mA symmetrical drive

50uA (typical) internal pull-up

50uA (typical) internal pull-down

Analog input

Analog output

AIO

Analog bi-directional

ICLK

Crystal oscillator input pin

OCLK

Crystal oscillator output pin

TABLE 2-5:

SYSTEM AND POWER SIGNALS (CONTINUED)

Pin No.

Name

Symbol

Buffer

Type

# Pins

Description

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