FLASH

AS8F128K32

AS8F128K32

Rev. 2.8 01/10

Micross Components reserves the right to change products or specifications without notice.

17

FIGURE 13: Alternate CEx\ Controlled Write Operation Timings

NOTES:

1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7\ = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

ERASE AND PROGRAMMING PERFORMANCE

TYP

1

MAX

2

UNIT

Chip/Sector Erase Time

1.0

15

sec

Excludes 00h programming prior to erasure

4

Byte Programming Time

14

1000

µs

Chip Programming Time

3

1.8

12.5

sec

LIMITS

COMMENTS

PARAMETER

Excludes system-level overhead5

NOTES:

1. Typical program and erase times assume the following conditions: 25° C, 5.0 V V

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the

maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for

further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1 for further information on

command definitions.

6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase