SSRAM

AS5SP512K36

AS5SP512K36

Rev. 3.0 10/13

Micross Components reserves the right to change products or specifications without notice.

1

Plastic Encapsulated Microcircuit

18Mb, 512K x 36, Synchronous SRAM

Pipeline Burst, Single Cycle Deselect

FEATURES

 Synchronous Operation in relation to the input Clock

 2 Stage Registers resulting in Pipeline operation

 On chip address counter (base +3) for Burst operations

 Self-Timed Write Cycles

 On-Chip Address and Control Registers

 Byte Write support

 Global Write support

 On-Chip low power mode [powerdown] via ZZ pin

 Interleaved or Linear Burst support via Mode pin

 Three Chip Enables for ease of depth expansion without

Data Contention.

 Two Cycle load, Single Cycle Deselect

 Asynchronous Output Enable (OE\)

 Three Pin Burst Control (ADSP\, ADSC\, ADV\)

 3.3V Core Power Supply

 3.3V/2.5V IO Power Supply

 JEDEC Standard 100 pin TQFP Package

 Available in Industrial, Enhanced, and Mil-

Temperature Operating Ranges

GENERAL DESCRIPTION

The AS5SP512K36 is a 18Mb High Performance

Synchronous Pipeline Burst SRAM, available in multiple

temperature screening levels, fabricated using High

Performance CMOS technology and is organized as a

512K x 36 array. It integrates address and control registers,

a two (2) bit burst address counter supporting four (4)

double-word transfers. Writes are internally self-timed and

synchronous to the rising edge of clock.

The AS5SP512K36 includes advanced control options

including Global Write, Byte Write as well as an

asynchronous output enable. Burst Cycle controls are

handled by three (3) input pins, ADV\, ADSP\ and ADSC\.

Burst operation can be initiated with either the Address

Status Processor (ADSP\) or Address Status controller

(ADSC\) inputs. Subsequent burst addresses are generated

internally in the system’s burst sequence control block and

are controlled by the Address Advance (ADV\) control

input.

Parameter

Symbol

200Mhz

166Mhz

133Mhz

Units

Cycle Time

tCYC

5.0

6.0

7.5

ns

Clock Access Time

tCD

3.1

3.5

4.0

ns

Output Enable Access Time

tOE

3.1

3.5

4.0

ns

Fast Access Times

100-PIN TQFP

PINOUT

(3-CHIP ENABLE)

Block Diagram

CONTROL

BLOCK

BURST CNTL.

Address

Registers

Row

Decode

Column

Decode

Memory Array

x36

SBP

I/O Gating and Control

Output

Register

Input

Register

CLK

CE1\

CE2

CE3\

BWE\

BWx\

GW\

ADV\

ADSC\

ADSP\

MODE

A0-Ax

DQx, DQPx

Output

Driver

❑ Synchronous Pipeline

Burst

❋ Two (2) cycle load

❋ One (1) cycle

de-select

❋ One (1) cycle latency

on Mode change

OE\

ZZ